1. Technical Field
This disclosure relates to an On Die Termination (ODT) circuit, and more particularly, to an ODT circuit which has improved high frequency performance, and can be used as a data output terminal.
2. Description of the Related Art
On Die Termination (ODT) technology has been developed to minimize signal reflection, distortion, or the like in an interface between a system and a memory to improve signal integrity (SI). Signal reflection has a negative influence on signal integrity. In particular, in a memory system supporting a high-speed operation, signal reflection has a more negative influence on signal integrity. In order to suppress such signal reflection, lines for transmitting signals between a system and a memory can be terminated by a termination resistor.
In general, in a memory system, the input/output (I/O) terminals of a memory controller or a memory can be implemented with an ODT circuit. The ODT circuit can be terminated by a termination resistor, where the resistance of the termination resistor is set to match the impedance of transmission lines.
In the case where an ODT circuit is used in a semiconductor memory device, the following items should be satisfied. First, the value of additional capacitance should be small. If the values of a junction capacitance or a parasitic capacitance are large, when a high frequency signal is input to the ODT circuit, the termination function of the ODT circuit deteriorates and signal attenuation becomes significant.
Second, the linearity of impedance should be maintained. That is, it is desirable to have a constant impedance value is maintained over a wide frequency range. If the impedance value changes sharply, signal attenuation can occur when an input signal having higher frequency components is received.
Third, the ODT circuit should be capable of being quickly turned on or off. For example, in the case of a dynamic random access memory (DRAM), or other memory device to/from which data is received/transmitted through a single data pin, an ODT circuit has to be quickly turned on or off according to whether the memory device is performing a read or a write operation.
FIG. 1A is a circuit diagram of a conventional ODT circuit 100. The conventional ODT circuit 100 includes a P-channel metal-oxide-semiconductor (PMOS) transistor P100 and a resistor R. The PMOS transistor P100 has a gate to which a ground voltage VSS is applied, a drain to which a supply voltage VDDIO is applied, and a source coupled to a first end of a resistor R. A second end of the resistor R is coupled to an input/output terminal (I/O) of a semiconductor memory device.
The ODT circuit 100 illustrated in FIG. 1 has a problem in that a parasitic capacitance component increases when the performance of the PMOS transistor P100 deteriorates. Also, if the amplitude of an input signal increases, the linearity of impedance can deteriorate since the PMOS transistor P100 transits from a triode region to a saturation region.
FIG. 1B is a circuit diagram of another conventional ODT circuit 150. The conventional ODT circuit 150 further includes an N-channel metal-oxide-semiconductor (NMOS) transistor N150, in order to solve the problem of the ODT circuit 100 illustrated in FIG. 1A. That is, in the ODT circuit 150, a first circuit, in which a PMOS transistor P150 is serially coupled to a resistor R1, is coupled in parallel to a second circuit in which an NMOS transistor N150 is serially coupled to a resistor R2.
In the case of FIG. 1B, since the ODT circuit 150 further includes the NMOS transistor N150, the ODT circuit 150 has an improved linearity of impedance, compared to the ODT circuit 100 illustrated in FIG. 1A. However, the ODT circuit 150 also still has the problem that the parasitic capacitance component increases.
FIG. 2A is a circuit diagram illustrating a case where the ODT circuit 100 (denoted by reference number 200 in FIG. 2A) illustrated in FIG. 1A is used as an output terminal. Inverted data /DATA is input to the gate of a PMOS transistor P200 of the ODT circuit 200. The ODT circuit 200 is configured to output the data /DATA through an output terminal OUT, while performing an ODT operation using a resistor R whose resistance matches the impedance of a transmission line.
FIG. 2B is a circuit diagram illustrating another case in which the ODT circuit 150 (denoted by reference number 250 in FIG. 2B) illustrated in FIG. 1B is used as an output terminal. Inverted data /DATA is input to the gates of a PMOS transistor P250 and an NMOS transistor N250. The ODT circuit 250 is configured to output the data /DATA through an output terminal OUT, while performing an ODT operation using resistors R1 and R2 whose resistances match the impedance of a transmission line.
Conventionally, in a semiconductor memory device, an ODT circuit for performing an ODT operation is used as an output terminal of the semiconductor memory device. However, when the ODT circuit is used as an output terminal, the problem as described above occurs.